| 摘要 |
PURPOSE:To eliminate the need for complex address control by using a FIFO memory matrix and adding the start terminal and the end terminal of the paralleling signal of plural channels to the just rear of a preceding channel and the just front of a following channel respectively. CONSTITUTION:An input from a terminal 11 is commonly supplied to FIFO memories 112 and 121 of a first row, a second column and a second row, a first column of a memory matrix 100, and the input from a terminal 12 is commonly supplied to FIFO memories 113, 112 and 131 of the first row, a third column, the second row, the second column and a third row, the first column. The input from a terminal 13 is commonly supplied to FIFO memory 123, 132 and 141 of the second row, the third column, a third row, the second column and a fourth row, the first column, and the input from a terminal 14 is commonly supplied to FIFO memories 133 and 142 of the third row, the third column and the fourth row, the second column respectively. Thus, the complex address control can be made unnecessary, the overlapping part adding processing of a screen dividing signal can be executed, the constitution of the peripheral circuit of the memory can be simplified, and a circuit scale can be reduced. |
