| 摘要 |
PURPOSE:To produce a quick answer even to a misaccess by providing a decoder to send an answer back to a CPU even though the object corresponding to an access signal received from the CPU is not included in a device. CONSTITUTION:An address decoder 2 receives the address signals A0-An from a CPU 1 and transmits the signal, the inverse of CS. A decoder 5 decodes said signal CS and makes an access to a register 10 to transfer the stored data. The end of the transfer is given in reply to the CPU 1 via an OR circuit 6, a delay circuit 7 and a NOR circuit 8. The decoder 2 outputs the signal, the inverse of CS which is decided by the decoder 5 even when the address data A0-A2 have errors. In this case, the output of a terminal 7' includes no storing part of the register 10 to receive an access. In such a case, however, an abnormal access detecting signal 9 is outputted from the terminal 7' and informed to the CPU 1. In such a constitution, a quick answer is obtained even to a misaccess and the CPU processing efficiency is improved. |
