发明名称 JFET ACTIVE LOAD INPUT STAGE
摘要 An active load circuit for operational amplifiers and the like is described which provides an improved common mode rejection ratio and common mode voltage range, and alleviates transistor saturation and cut off problems during maximum slew rates. Drive currents from the operational amplifier or other circuit are transmitted directly through respective load resistors, thereby reducing voltage offsets which degrade common mode rejection ratio. At the same time the absolute voltage levels at the operational amplifier or like circuit are reduced, thereby increasing the common mode voltage range. A pair of active load transistors are supplied with current from current sources independent of the amplifier transistors, and deliver their respective currents to the same resistors which receive the amplifier currents. An output is taken from one of the load transistors without connecting to either of the amplifier transistors.
申请公布号 DE3567135(D1) 申请公布日期 1989.02.02
申请号 DE19853567135 申请日期 1985.03.19
申请人 PRECISION MONOLITHICS INC. 发明人 BUTLER, JAMES R.
分类号 H03F3/45;(IPC1-7):H03F3/45 主分类号 H03F3/45
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