| 摘要 |
In order to test circuits which are integrated on chips, one special test chip (TEB) is provided per chip to be tested, which test chip is arranged geometrically immediately adjacent to the chip (PR) to be tested. The test chip (TEB) produces test patterns for the chip to be tested, receives the response signals emitted by the chip to be tested on the basis of the test patterns, and analyses these response signals. As a result of the chip (PR) to be tested and the test chip (TEB) being immediately adjacent to one another, electrically reliable and mechanically robust contact-making is achieved. At the same time, the test patterns can be applied at the operating frequency of the chip to be tested and, in addition, a large number of chips on one wafer can be tested in parallel. <IMAGE> |
