| 摘要 |
<p>The system switches packets of various lengths, dividing them up into packet blocks having a constant length. The system comprises input circuits (CE1 to CE8) for synchronising the packets delivered by incoming time-division multiplexes (E1 to E8) and detecting, in packet headers, labels and words indicating packet length, an input rotation matrix (MRE) and an output rotation matrix (MRS) effecting parallel-diagonal and diagonal-parallel conversions, and a buffer memory (MP) between the matrices and in which the packets divided into diagonalised blocks are temporarily stored. A switching and label conversion circuit detects the labels (ET) of packets from the first words (B1) of packet blocks delivered by the input matrix so as to interpret the labels and order the switching of the packets to outgoing multiplexes (S1 to S8). A packet read control circuit (CLP) calculates the address in the buffer memory of each of the blocks of a packet to be transmitted in an outgoing multiplex, as a function of the address of a cell in the buffer memory having stored the first block of the packet and of the word indicating packet length. <IMAGE></p> |
