| 摘要 |
<p>PURPOSE:To transfer data at high speed by dividing a bus so as to divide plural peripheral circuits into plural groups by a control signal from a CPU. CONSTITUTION:The titled processor consists of the CPU 1, the peripheral circuits 3-8, the buses 2a-2c and switches for opening and closing parts between these buses, the bus is divided correspondingly to the three groups 20-22, for instance, and the parts therebetween are connected by the switches 9, 10 controlled by the CPU 1. Namely, the buses 2a-2c are divided into plural to control a connection between the respective buses according to a control mode. Accordingly, at the time of executing a DMA (Direct Memory Access) transfer, in the CPU 1 itself, the parallel execution of a processing routine except the access of a hardware relating to the DMA transfer can be attained. Thereby, the high speed operation can be realized.</p> |
