| 摘要 |
PURPOSE:To miniaturize by forming the source, region, a drain region of a lower gate MIS FET in a self-aligning manner with a gate electrode. CONSTITUTION:A polycrystalline silicon is formed on a silicon oxide insulating film 101, and a gate electrode 102 is formed. A first thin film 105 is coated with an organic second thin film 105. The electrode 102 is exposed by etching. The film 105 is separated, and a phosphorus-doped silicon layer 106 is formed. The layer 106 and a first thin film 104 extend partly on the electrode 102 and both side regions of the electrode 102 to be selectively retained, and the photoresist is removed. It is heat treated at 900 deg.C for 30 min in a nitrogen atmosphere to diffuse the boron in the film 104 in the layer 106 to form a source region 107a and a drain region 107b in a self-aligning manner with respect to the electrode 102. |
