| 摘要 |
PURPOSE:To allow a reception side to recognize an output of a write signal in a disadvantageous timing and to preclude the possibility of mis-reception due to being unnoticed of the said error by monitoring a timing of the write signal input and inhibiting the load of data if the write signal is retarded and not inputted till the next load signal is inputted. CONSTITUTION:If a delay is caused in the write signal WS, a load signal is generated and since no write signal WS is inputted till the next load signal is generated, a load inhibition circuit 6 detects it to inhibit the input of a load signal to a shift register 3. Thus, the shift register 3 does not load a new data to continue the output of the stop bit signal. Thus, the reception side detects the fault of conversion depending on the stateof the outputted serial data and the overlook of the communication of a serial data with wrong timing is prevented. |
