| 摘要 |
A sample hold circuit consists of a variable gain voltage-to-current converter and an integration circuit which are connected in series. The conversion gain of the variable gain voltage-to-current converter varies in response to a level of a sampling pulse and one of a follow mode and a hold mode is selected in response to the level of the sampling pulse. In the follow mode when the level of the sampling pulse is high, the conversion gain of the converter is set to the maximum and an output signal of the integration circuit follows up an analog input signal which is inputted into the converter. In the hold mode when the level of the sampling pulse is low, the conversion gain of the converter is set to the minimum and the level of the output signal of the integration circuit is held at a level just before the hold mode is selected.
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