| 摘要 |
A system bus control circuit associated with a central processing unit that generates control signals and in which the control circuit is constructed of a timing circuit having a plurality of successively connected timing stages constructed of data flip-flops for respectively generating sequentially time-displaced timing control signals. A gate array is employed for providing additional logic gating. The control signal from the central processing unit coupled to one group of input lines of the gate array. A second group of input lines to the gate array are coupled from the timing circuit and in particular the individual stages of the timing circuit. The output lines from the gate array generate timing signals that control data bus operation.
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