RAM with dual precharge circuit and write recovery circuitry

摘要

A memory is written via data lines which are driven by a write driver. The data lines are coupled to a selected bit line pair as determined by a column address. The data lines are driven to a logic state representative of a data input signal by a write driver. The write driver is enabled during the presence of a write enable pulse. The write enable pulse is generated in response to a read mode to write mode transition and also in response to a transition of the data input signal. The data lines are precharged in response to a transition of the data input signal that occurs during the write mode.