| 摘要 |
<p>PURPOSE:To attain a packet switch applying R/W common arbitration while a multistage switch is constituted efficiently by outputting an access enable signal when both write/read arbiters are selected by a priority arbiter control circuit and other arbiter outputs a signal representing the absence of an access request input or an access enable output. CONSTITUTION:A priority arbiter control circuit 44 is provided and an access enable signal is outputted when both the write/readout arbiters 41, 42 are selected by the priority arbiter control circuit 44 and the other arbiter outputs a signal representing the absence of the access enable output. Thus, when the request is consecutive, since at least a half of the memory cycle is guaranteed to allocate the write or readout with consecutive request, the arbitration of the R/W common is attained efficiently.</p> |
