| 摘要 |
PURPOSE:To avoid the collision of data on a system bus by inhibiting the input of other bus request signals to an arbitrating means until an allowed bus master is through with use of the system bus. CONSTITUTION:A window is circulated by a clock pulse received from a clock generating circuit 25 and the AND circuits 21 are successively activated. Then an access detecting circuit 27 checks the presence or absence of the bus request signals BREQ1-8. When a bus request signal is detected, the circulation of the window is stopped. Then the AND output obtained between the bus request signal BREQn received from a bus master that tried a bus request and the window output is outputted as a bus preference input BPRNn. The input BPRNn is outputted continuously until an access acknowledge signal XACK is received from a master receiving an access request. The window is circulated again with reception of the signal XACK and a detecting action is started again for the bus request. |
