| 摘要 |
PURPOSE:To reduce the occupying area of a memory cell by forming part of a trench sidewall for forming a transistor in contact with a dielectric isolation region. CONSTITUTION:A trench 9 is formed on a substrate made of a P<+> type layer 1 and a P-type layer 2, and a vertical MOS transistor is formed at its top with a polysilicon film 7 as a gate electrode, N<+> type layers 8, 8' as source, drain, and a gate oxide film 6. A thick SiO2 film 3 for electrical dielectric isolation of each memory cell is provided in contact with right and left trench sidewalls. An N<+> type layer 8 which becomes a bit line is present between dielectric isolation films 3', 3'' formed on the side opposite to the film 3 and the trench sidewalls. Accordingly, the trenches can be disposed near twice as small as the width of the layer 8, thereby reducing the occupying area of the memory cell. |
