发明名称 HARDWARE LOGICAL SIMULATOR
摘要 PURPOSE:To easily detect the coverage of simulation by writing and reading prescribed data in and out of an address of a storage means determined according to the state of a specified signal group after variation at the time of simulation. CONSTITUTION:A specifying means 2 which specifies a signal group in a simulation model and an incorporating means 3 which generates a storage means inputting the specified signal group as an address and incorporates it in the model are provided. Further, a writing means 1 which writes the prescribed data in the address of the storage means determined according to the state of the state of the signal group specified by the specifying means 2 after the variation at the end of simulation and a reading means 5 which reads the stored data are provided. The storage data in the storage means are checked after the end of the simulation and its unwritten address shows a combination where simulation is not performed. Consequently, the combination where no simulation is performed is regarded as a target, a repeated test case is eliminated, and efficient simulation for sufficient logical verification becomes possible.
申请公布号 JPS6426243(A) 申请公布日期 1989.01.27
申请号 JP19880034027 申请日期 1988.02.18
申请人 NEC CORP 发明人 KURASHITA MASAHIRO;NOMIZU NORINAGA
分类号 G06F11/25;G06F17/50;G06F19/00 主分类号 G06F11/25
代理机构 代理人
主权项
地址