发明名称 PLL CIRCUIT
摘要 PURPOSE:To set the phase deviation at the time of detecting lock with high accuracy by adopting the constitution such that the output pulse of a phase comparing circuit is applicable to a clock input terminal of a flip-flop circuit and applicable also to a terminal D via a delay circuit in an optical disk test system. CONSTITUTION:Output pulses PU, PD obtained from a phase comparating circuit 1 are fed to the clock input terminal of a flip-flop circuit 8 via a logic circuit 6 and also fed to a terminal D of the flip-flop circuit 8 via a delay circuit 7. The state of signal at the terminal D is fetched at the leading edge of the pulse signal fed to the clock input terminal in the flip-flop circuit 8. An output signal SL obtained from the flip-flop circuit 8 is used as a lock detection signal. In such a case, a changeover switch 9 is switched in response to the input frequency and the output of a prescribed flip-flop circuit is selected, then the locking state is always detected at a constant phase deviation even when the input frequency is changed.
申请公布号 JPS6424630(A) 申请公布日期 1989.01.26
申请号 JP19870181980 申请日期 1987.07.21
申请人 YOKOGAWA ELECTRIC CORP 发明人 HANAWAKA MASUO
分类号 H03L7/095;G11B7/00;G11B7/005;G11B20/14;H03L7/08 主分类号 H03L7/095
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