发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To prevent spurious radiation with a comparatively simple circuit constitution by providing a signal suppressing circuit means eliminating a frequency component being (n)-fold of the frequency of an input signal, and further, as required, 1/n-fold between a low pass filter and a voltage controlled oscillation circuit VCO. CONSTITUTION:The signal suppression circuit 3a composed of an adder circuit 32 and a delay circuit 31 whose delay time (tau) is 1/2fr is provided on a post- stage of a phase comparator 11 and a low pass filter 12, and its output signal is applied to the VCO 14. A frequency divider 15 is connected between the VCO 14 and the phase comparator 11. The input frequency 10MHz is FM- modulated by the VCO 14 to become an output signal SOUT in a frequency of 360MHz. On the other hand, a spurious component is outputted at a position deviated by 10MHz at both sides of the frequency of 360MHz, but it is removed.
申请公布号 JPS6424632(A) 申请公布日期 1989.01.26
申请号 JP19870179935 申请日期 1987.07.21
申请人 FUJITSU LTD 发明人 KOBAYASHI FUMIHIKO
分类号 H03L7/093;H03L7/08;H03L7/18 主分类号 H03L7/093
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