| 摘要 |
PURPOSE:To enable the high degree integration, by stacking three-dimensionally capacitor plates composed of polysilicon. CONSTITUTION:A P-type or an N-type silicon substrate, e.g., is used for a semiconductor 1. The title capacitor has a 4-layer polysilicon structure. Polysilicon B10 and A9, and polysilicon B10 and C11 are electrically insulated with an oxide film side-wall 7. The polysilicon A9 and the polysilicon C11 are brought into contact with each other by using polysilicon D12. Electric charge is stored in the polysilicon A9 and C11. Polysilicon E13 is the gate of a MOS transistor, and a drain 1D comes into contact with the polysilicon A9. By increasing the area of a capacitor plate in this fashion, the remarkably high degree integration is enabled as compared with prior planer type capacitors. |
