| 摘要 |
PURPOSE:To improve the degree of integration by forming a first mask in the alternate regions in which a wiring is to be formed on the layer on which wirings are to be formed, and forming, on the side walls of the first mask, a second mask which is in self alignment therewith and the size of which is defined by the etching amount, thereby defining the wiring spacing based on the etching amount of the second mask. CONSTITUTION:A first mask 12 is formed in the alternate regions in which a gate electrode is to be formed on a layer 5 where the gate electrodes are to be formed, and on the side walls of the first mask 12, a second mask 13A is formed the size of which is defined by the etching amount. After removing the first mask 12 with this second mask 13A, a third mask 16 is formed with the second mask 13A in the regions where a wiring is to be formed on the layer where a gate electrode is to be formed using this third mask 16, the second mask 13A is removed, and the part between the layer 5 where a gate electrode is to be formed and the regions in which a gate electrode is to be formed is removed, thereby forming a gate electrode 5A of a memory cell. With this, the gate electrode 5A spacing can be defined by the etching amount of the second mask 13A and this spacing can be reduced, so that the occupation area of the region in which the memory cell is to be formed can be reduced, thereby to improve the degree of integration of semiconductor integrated circuit devices. |
