发明名称 VARIABLE DELAY LINE
摘要 PURPOSE:To obtain a delay time stable to a temperature change by correcting a voltage impressed to a variable capacity diode in a variable delay line element serially connected to a buffer circuit with a temperature characteristic reverse to the temperature characteristic of the buffer circuit. CONSTITUTION:To plural taps provided on respective wound inductance elements L, one edge of a variable capacity diode Dv is connected, a variable delay line element DL is formed and by the voltage impressed to the diode Dv, the delay time of the element DL is changed. The element DL is serially connected through an inverter circuit (buffer circuit) I and a variable delay line is constituted. When an ambient temperature rises, the propagation delay time of the inverter circuit I is increased, a control signal from a signal source DAC is increased in a negative direction by a correcting circuit 7 only for the increased part, and thereafter, it is impressed to the diode Dv, and therefore, even when the ambient temperature is changed, the propagation delay time correction of the inverter circuit I can be automatically executed.
申请公布号 JPS6422104(A) 申请公布日期 1989.01.25
申请号 JP19870178500 申请日期 1987.07.17
申请人 ELMEC CORP 发明人 KAMETANI KAZUO
分类号 H03H7/30;H03K5/131;H03K5/133;H03K5/14 主分类号 H03H7/30
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