发明名称 |
Generator for generating a bus cycle end signal for debugging operation. |
摘要 |
<p>In a debugging microprocessor having a function of elongating a bus cycle in response to an external ready signal and used in a microprocessor development support system having a function capable of tracing and analyzing the result of execution, there is provided a generator for generating a bus cycle end signal to the microprocessor development support system. The generator comprises an ready detection circuit receiving an external ready signal, a clock signal and an enable signal which is rendered active only when the debugging microprocessor is in a condition capable of accepting data. The ready detection circuit operates to detect the status of the external ready signal at a timing defined by a clock appearing when the enable signal is active, so as to generate an internal ready signal if the external ready signal is active. A control circuit is connected to receive the internal ready signal for generating a signal indicative of an end of the bus cycle for a predetermined time of period starting from a next clock state. This bus cylce end signal is outputted to an external of the debugging microprocessor.</p> |
申请公布号 |
EP0300507(A2) |
申请公布日期 |
1989.01.25 |
申请号 |
EP19880111957 |
申请日期 |
1988.07.25 |
申请人 |
NEC CORPORATION |
发明人 |
SHOUDA, MASAHIRO C/O NEC CORPORATION |
分类号 |
G06F11/28;G06F11/36;G06F15/78 |
主分类号 |
G06F11/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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