发明名称 |
Address buffer circuit for a dram |
摘要 |
A DRAM has an input address buffer in which the first stage is a NOR gate. The output of the NOR gate is clocked to a latch which is preset to the slow condition of the NOR gate. The NOR gate is clocked separately from the clocking of the output of the NOR gate to the latch. A refresh control circuit has an output which is also clocked to the latch. The latch provides an internal address signal for selecting a word line. The internal address signal is representative of the output of the NOR gate when the DRAM is running a data cycle and is representative of the output of the refresh control circuit when the DRAM is running a refresh cycle.
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申请公布号 |
US4800531(A) |
申请公布日期 |
1989.01.24 |
申请号 |
US19860944784 |
申请日期 |
1986.12.22 |
申请人 |
MOTOROLA, INC. |
发明人 |
DEHGANPOUR, SAM;PELLEY, III, PERRY H. |
分类号 |
G11C11/408;(IPC1-7):G11C7/00;G11C8/00 |
主分类号 |
G11C11/408 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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