| 摘要 |
A semiconductor device having one or more first non-volatile memory transistors and a detector having a second non-volatile memory transistor with which a charge level written in the first transistor is safeguarded and corrected, if necessary, by a suitable, incorporated bias voltage between source zone and control electrode and/or a margin fixed by an incorporated difference in threshold voltage. A further non-volatile memory transistor may be present with which there is detected, during writing, erasing or rewritting, whether the desired charge level in the first transistor is reached and the charge transport is to be terminated.
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