| 摘要 |
A broadband/baseband interface device for passing data packets accurately and as swiftly as possible from an interface of one medium, (e.g., Ethernet) through to an interface of another medium (e.g., RF modem) in near real time. Incoming data on the broadband medium is received both at the data RAM where it is stored and in a CRC detection module which performs cyclic redundancy checking calculations upon the packet, sending signals upon calculating positive results to both a CRC counter and to a CRC RAM. When the receipt of a packet from the broadband medium is ended, the signal ends, leaving an unpredictable collection of "dribble" bits. Since each positive CRC calculation was noted by the CRC detector and its indicator was stored in an address in the CRC RAM, the exact end of the packet in the data RAM can be positively identified and distinguished from the random "dribble" bits. The counter is then decremented during the baseband transmission process until zero is reached, corresponding to and identifying the end of the packet. At that time, the baseband media driver is disabled.
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