发明名称 TEST PATTERN GENERATION METHOD FOR LOGIC CIRCUIT
摘要 PURPOSE:To improve the performance of a test pattern automatic generating program by giving a symbol for showing a fact that a '0' state cannot be set, and a symbol for showing a fact that a '1' state cannot be set, to each signal line. CONSTITUTION:For instance, in a process for generating a test pattern for detecting certain fault, it is supposed that a signal line 3 is determined to a symbol U (neither a '0' state nor a '1' state cannot be set). Also, it is supposed that it is desired to a set a state of a signal line 7 to '1'. As a result, by an AND calculation of the symbol U of the signal line 3 and a symbol X (can be set to both a '0' state and a '1' state) of a signal line 4, a symbol of a signal line 5 is determined as L by a arithmetic rule table shown in the table, therefore, it is known that even if a '1' state is requested to the signal line 5, it cannot be realized, and a '1' state is requested to a signal line 6. In such a way, the performance of a test pattern automatic generating program is improved.
申请公布号 JPS6420465(A) 申请公布日期 1989.01.24
申请号 JP19870174632 申请日期 1987.07.15
申请人 HITACHI LTD 发明人 HAYASHI TERUMINE;HATAKEYAMA KAZUMI;IKEDA KOJI
分类号 G01R31/317;G01R31/28;G06F11/22;G06F17/50 主分类号 G01R31/317
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