| 摘要 |
<p>PURPOSE:To reduce the number of the elements of a drive circuit and to enhance printing quality, by a method wherein the number of bits of a shift register are set to 1/n as compared with the number of output drivers and data at intervals of (n-1)-bits are inputted n-times as input data and distributed to the output drivers by a selection gate signal to be outputted from the output drivers at intervals of n-bits. CONSTITUTION:A clock signal, data, a latch signal, an output control signal and a selection gate signal are respectively inputted to the input terminals 21, 22, 23, 25, 24 of a circuit. Data of bits in odd numbers are sent at a part 1 to be taken in a latch circuit 12 at a position 2. A selection gate 13 selects the bits in odd numbers of an output driver and data of bits in odd numbers are outputted from the output driver 15 of bits in odd numbers at a part 2. Data of bits in even numbers are sent at a part 3 to be taken in the latch circuit 12 at a position (b). The selection gate 3 selects the output driver 15 of bits in even numbers and data of bits in even numbers are outputted from the output driver 15 of bits in even numbers. Adjacent dots are not simultaneously outputted and a shift register 11 and the latch circuit 12 become 1/2 as compared with conventional ones.</p> |
