发明名称 PSEUDO SYNCHRONIZING DETECTING CIRCUIT
摘要 PURPOSE:To prevent a demodulating circuit from entering the pseudo synchronizing state by detecting it that the demodulating circuit applying synchronization demodulation falls into the pseudo lock state from an input signal to control a recovered carrier. CONSTITUTION:An absolute value circuit 105 supplies absolute value to an output signal of a demodulating circuit 104 and supplies its output to a mean circuit 106, where a noise component is compressed and the signal component is extracted. A square circuit 107 applying square operation estimates a value nearly equal to signal power and supplies it to a subtracting circuit 110 and an S/N detecting circuit 111 as an output. On the other hand, the square circuit 108 obtains the total power of the output signal of the circuit 104 and supplies it to a mean circuit 109. The output of the circuit 109 is set sum of signal power and noise power and the result is given to the circuit 110. The circuit 110 estimates the noise power by the subtraction and outputs it to the circuit 111. The circuit 111 detects the demodulation signal power versus noise power (S/N) by the arithmetic operation. The control circuit 112 monitors the output state of the circuit 111 to control the VCO 102, thereby maximizing the output value.
申请公布号 JPS6418339(A) 申请公布日期 1989.01.23
申请号 JP19870175658 申请日期 1987.07.14
申请人 NEC CORP 发明人 OTANI SUSUMU
分类号 H04L27/227;H04L27/22 主分类号 H04L27/227
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