发明名称 PNP LOAD TYPE MEMORY CELL
摘要 PURPOSE:To prevent a breakdown strength from decreasing without complicating wirings by covering the base region of a lateral PNP transistor through an insulator with the wiring conductor of a word line to set the gate of a parasitic MIS transistor to the same potential as that of the word line. CONSTITUTION:The emitter of a lateral PNP type transistor is composed of a first P-type region 1, the collector is composed of a second P-type region 2, and the base is composed of an N-type region 4. On the other hand, the emitter of an NPN type transistor is composed of emitter regions 5, 6, the collector is composed of an N-type region 4, and the base is composed of a second P-type region 2. A wiring layer 11 of a word line electrode is contacted with the region 1 at a word line electrode W, and covers through an insulating film 9 the region 4 of the section which becomes the base region of the PNP type transistor. With this configuration, the word line and the gate of the parasitic MIS transistor becomes the same potential, and the breakdown strength of the PNP type transistor is enhanced.
申请公布号 JPS6417461(A) 申请公布日期 1989.01.20
申请号 JP19870172926 申请日期 1987.07.13
申请人 NEC CORP 发明人 SATO HIROAKI
分类号 H01L21/76;G11C11/40;G11C11/41;H01L21/331;H01L21/8229;H01L27/06;H01L27/10;H01L27/102;H01L29/72;H01L29/73;H01L29/732 主分类号 H01L21/76
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