发明名称
摘要 <p>PURPOSE:To drop a spare bit to exchange a clock at the inside of a station through a simple circuit by recognizing a frame which is selecting and reading plural buffer memories of the transmission line side at the inside of the station. CONSTITUTION:At the inside of a station, buffer memories 5 and 6 are selected alternately by a selector 7 to read out frames A and B. A counter 9 forms a drop pulse by a selector signal SR and a clock of the intra-station side of a clock pulse generating circuit 8. a drop pulse for a spare bit X1 of the frame A is obtained by having an AND between the first one of eigth intra-station side clocks corresponding to the frame A and the signal SR. Then said drop pulse is supplied to a clock input terminal of an FF circuit F1 of a spare bit extracting circuit 10. The bit X1 is dropped since the frame A is supplied to a data input terminal of the circuit F1 from the memory 5 via the selector 7. so is with spare bits X2 and Y1-Y5 of the frame B.</p>
申请公布号 JPS643102(B2) 申请公布日期 1989.01.19
申请号 JP19830226307 申请日期 1983.11.30
申请人 FUJITSU LTD 发明人 YO KATSUHIRO;SHINODA RYOICHI;YAMAZAKI HAJIME;SHIMIZU KAZUO
分类号 H04J3/06;H04J3/07;H04L7/00 主分类号 H04J3/06
代理机构 代理人
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