| 摘要 |
PURPOSE: To warrant a maximum timing margin by providing a means that compares the output of a latch or non-clock data with the output of a clock latch to compare phases. CONSTITUTION: The circuit is provided with input comparators 10, 12 having complementary outputs, a delay element 14, set-reset latches 16, 18, a phase/ frequency comparator 20, a loop filter 22 and a voltage controlled oscillator(VCO) 24 and a single trigger D type FF 26. In the case that a single phase offset is in existence, when a frequency of the VCO 24 is equal to an input data rate of a line 28, outputs U, D of the comparator 20 generate a pulse to change a frequency of the VCO 24 in the direction of correcting the phase offset. When a frequency of the VCO 24 is not equal to the input data speed, an incoming data signal to a line 28 is compared with the modified same data signal counted again by a clock signal from the VCO 24 to detect a phase of the loop. |
