发明名称 DATA MULTI-DIVISION TYPE ARITHMETIC UNIT
摘要 PURPOSE:To eliminate the need of the calculation pre-processing and the calculation post-processing for a partial calculation, and to simplify the control, by providing a means for switching lower carry and upper carry positions to arbitrary length, on a carry look-ahead circuit. CONSTITUTION:A lower carry input signal of a carry look-ahead circuit is connected to the lowest bit of a partial data position and switched to a carry signal from the lower one of all the data. Also, an upper carry output signal is outputted from the uppermost bit of the partial data position, and switched to a carry signal to the upper one of all the data. For instance, when the data is constituted of a 32 bit data and divided into two, and two data of 16 bits are handled, the data of 16 bits extending from the data A0 to A15 of an arithmetic circuit 10, and the data of 16 bits extending from B0 to B15 are inputted, and in case of executing the calculation, the lower carry input is executed to '0' bit of a CLA (carry look-ahead), and an upper carry of 15 bits is outputted. In such a way, the pre-processing and the post-processing of the partial data calculation are not required.
申请公布号 JPS6414636(A) 申请公布日期 1989.01.18
申请号 JP19870168722 申请日期 1987.07.08
申请人 HITACHI LTD;HITACHI ENG CO LTD 发明人 MATSUO SHIGERU;KATSURA AKIHIRO;KIKUCHI MASAHIKO
分类号 G06F7/50;G06F7/508 主分类号 G06F7/50
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