| 摘要 |
PURPOSE:To eliminate the need for 2 ports for line control and a DMA controller by providing 2 systems of memory devices and processor buses to improve the processing capability of store and forward switching processor. CONSTITUTION:When an access request of a processor 1 is addressed to a program and data storage memory device 2A, a bus controller 8 separates a DMA system bus 5B from a processing system bus 5A to attain DMA transfer of data on a DMA system bus 5B in parallel with the access of the processor 1 to the memory device 2A. Thus, when the memory devices are divided into two systems and the buses are divided into two systems, since the processor 1 uses mainly the processing system bus 5A, the packet processing by the processor 1 and the DMA transfer of the packet on the DMA system bus 5B are executed almost parallel with each other thereby improving the processing capability.
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