| 摘要 |
PURPOSE:To enable the miniaturization of a chip without deteriorating the ON resistance and the breakdown voltage characteristics, by forming a source region in a well region by using an impurity introducing mask whose width is narrower than that of a first impurity introducing mask used for forming the well region. CONSTITUTION:On an N<+> substrate 1, an N-type layer 2 operating as a drain is formed. On the surface side of the N-type layer 2, a P-well region 3 is formed, on the central part of which a P<+> well region 4 is formed. The P-well region 3 is formed by introducing and diffusing P-type impurity. In this process, a first impurity introducing mask is used, in which a side wall 15a of SiO2 is arranged on the side part of a gate electrode 8. In a part from the P-well region 3 to the P<+> well region 4, an N<+> source region 5 is formed. On the P-well region 3 between the N<+> source region 5 and the N-type layer 2, a gate electrode 8 to induce a channel 6 is formed, via a gate insulating film 7. The N<+> source region 6 is formed by introducing and diffusing N-type impurity applying the gate electrode 8 to an impurity introducing mask. |
