| 摘要 |
<p>PURPOSE:To prevent the electron emission of a memory cell not selected by setting a column line corresponding to a memory cell block not selected via 2 sets of MOS transistors (TRs) at the time of writing erasure to a prescribed potential to apply enough writing/erasure. CONSTITUTION:A common source terminal VS and a signal A in an EEROM cell array is set in a high potential. The, for example, only a row line 11-1 is brought into 1 by a row decoder 12, MOS TRs 15-11, 15-14 are turned on by a column decoder 16 and only a signal CE1 of a column decoder 18 for writing is brought into 0. Then memory cells 10-111, 10-114 of the memory block are selected and writing/erasure is applied sufficiently without limitation to other memory cells via data input/output lines 14-1, 14-4. In this case, two sets of MOS TRs 19N1 and 19N4, and 20N1 and 20N4 are turned on and MOS TRs 15N1, 15N4 are turned off, the column lines 13N1, 13N4 of other non- selection memory block are charged to a high potential equal to that at a terminal VS and the emission of the electrons of the memory cells 10-N11, 10-N14 of the block connected to the row line 11 is prevented.</p> |
