| 摘要 |
PURPOSE:To facilitate the control of the delay time for the activation timing by connecting the MOSFET's of different current capacity in series between power sources and then applying the output signal and the signal sent from the input to the gate of MOSFET each. CONSTITUTION:When basic input clock inversion phiTTL of RAM shifts from H to L level and then enters the active period, MOSFETQ3 and Q6 become inconductive and the potential of node 2 begins to rise via MOSFETQ2. As a result, node 5 of MOSFETQ8 and Q9 connected in series between the power sources becomes L level, and MOSFETQ7 becomes inconductive with Q5 turned conductive. And activation timing signal phi1 begins to rise. When the rising of signal phi1 is over, signal P begins to rise. Signal P is then applied to the gate of FETQ8. The current capacity of FETQ9 is set larger than FETQ8, and at the same time the current capacity of FETQ7 is set larger enough than Q5. As a result, the rise of signal phi1 can be accelerated. The rise time of signal phi1 is adjusted through setting of the current capacity of Q8 and Q9, thus obtaining the necessary address setup time. |
