LEVEL CONVERSION CIRCUIT

摘要

In an ECL to CMOS converter circuit an ECL input signal is applied directly to the source electrode of a MOS transistor (MP1), and the gate electrode of the MOS transistor (MP1) is independently regulated by connection to a reference voltage that is connected to a current sink formed by a D.C. path to the negative CMOS voltage supply terminal. The drain electrode of the MOS transistor (MP1) is connected to the input of a CMOS inverter (MP3, MN3) to provide the necessary logic level shift. Another MOS terminal (MN1) provides a D.C. signal path by connecting the input of the CMOS inverter (MP3, MN3) to the negative CMOS voltage supply terminal.