| 摘要 |
PURPOSE:To reduce the erase time of memory content of a memory cell array, by providing a word line switching the connection to a ground potential to each bit line to control the switching with an erase signal. CONSTITUTION:Gates of transistors (TRs) QD, Q1... switching the connection to ground potential and a word line ERA for connection are provided at each bit lines 0.2..., and in driving the ERA with an erase word driver 3 to wbich an erase signal is applied, the lines 0.2... are grounded. Thus, in driving selectively word lines 0.1... via a row address decoder and a word line driver 1, the storage content of the memory cell array 0 is erased in a short time without accessing the address of all memory cells. |
