| 摘要 |
PURPOSE:To facilitate the coding of a PN code series of a parallel digital signal by storing a code pattern corresponding to the series code to be converted in a memory. CONSTITUTION:The circuit is designed such that read outputs B1, B2 of a memory 10 are selected to be 11 with inputs A1, A2 at 10 and outputs D1, D2 of 1-clock delay circuits 11, 12 at 00. That is, with 4-bit address inputs D1, D2, A1, A2 of the memory 10 at 0010, then '11' has only to be written in advance. The outputs B1, B2 (=11) are fed to the circuits 11, 12, where they are retarded by one clock and the 4-bit address input to the memory 10 is obtained the same as the bits of the input signals A1, A2. In selecting the inputs A1, A2 as 11, the 4-bit address input is 1111 and '11' is written in advance in the memory 10 corresponding to the 4-bit address input. Similarly, the content of the memory 10 in all combinations of the levels A1, A2 and D1, D2 is set similarly. |
