发明名称 CLOCK SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To attain the pull-in of a short time by detecting the presence or absence of the output of a full-wave rectifying circuit and selecting a constant voltage signal through a switching circuit when an output is not executed, in the clock synchronizing circuit of an N value PSK and QAM modulating system receiving side demodulator. CONSTITUTION:The clock component of respective base band signals P and Q of an N value PSK and QAM modulating wave is fetched by a full-wave rectifying circuit 1, processed by a loop circuit formed by a phase comparator 4, a switching circuit 8, an LPF5, a VCO 6, etc., through a synthesizing circuit 2 and a BPF3 and phase-locked-controlled. When the level of a clock component through the circuit 2 is detected and a clock component is absent, the circuit 8 is switched, a constant voltage from a constant voltage generating circuit 9 is supplied to a loop, and even when the clock component is absent, the pull out quantity does not become larger. As a result, the pull-in can always be executed in a short time.
申请公布号 JPS647714(A) 申请公布日期 1989.01.11
申请号 JP19870161264 申请日期 1987.06.30
申请人 NEC CORP 发明人 KOIZUMI YUTAKA
分类号 H03L7/14;H04L27/22;H04L27/38 主分类号 H03L7/14
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