| 摘要 |
<p>A video signal processing circuit for a VTR system is disclosed. In a special playback mode such as "STILL", "SLOW" and "QUICK" modes, a pseudo vertical synchronizing signal is supplied which has a train of pulses at a predetermined cycle proportional to one horizontal cycle. There are provided a detection circuit (13) for detecting the pseudo vertical synchronizing signal to produce a detection signal and a pulse separator (14) separating the train of pulses from the pseudo vertical synchronizing signal. When the detection signal is produced, a reproduced video signal is supplied to a clamping (9, 10, 11, 12, 520) circuit which clamps each synchronizing signal contained in the reproduced video signal at a predetermined level. When the detection signal is not produced, on the other hand, the separated pulses are transferred to the clamping circuit, and the clamping circuit is controlled to be made inoperative during the production period of each pulse.</p> |
