| 摘要 |
PURPOSE:To prevent soft ware errors by a method wherein a P-type layer is provided under an N<+> diffusion layer where a stacked capacitor connects to a switching transistor connect. CONSTITUTION:An upper electrode 12 is kept at a constant, prescribed voltage, and a lower electrode 10 is connected to a second conductivity type N<+> diffusion layer 5a through a contact hole 9. A switching MOS transistor is comprised of a gate oxide film 3, a gate electrode 4a, and source-drain diffusion layers 5a and 5b, and the gate electrode 4a extending over a neighboring memory cell serves concurrently as a word line 4b. The diffusion layer 5b of the switching transistor is connected to an aluminum bit line 15 through a contact hole 14. Under the N<+> diffusion layers 5a and 5b, there is a first conductivity type P-type layer 7 with its impurity concentration higher than that of a substrate 1. This design suppresses a depletion layer from extending from a diffusion layer to a semiconductor substrate and prevents carriers, generated in the presence of alpha rays, from flowing into the diffusion layer. |
