| 摘要 |
<p>PURPOSE:To reduce the number of components while any clock signal of a frequency can be stably switched by crossing the input and output of two D-FFs and preventing both outputs from being active simultaneously. CONSTITUTION:The input and output of D-FFs 11 and 12 are crossed. For this reason, the outputs of the D-FFs 11 and 12 do not go to an HI level simultaneously. Consequently, even when the frequency of clock signals C1 and C2 is in any relation, an always stable signal is outputted from an OR gate 19 and a succeeding circuit does not execute a malfunction. Since only two D-FFs are used, the number of parts is minimized.</p> |
