| 摘要 |
A CMOS binary equals comparator circuit suitable for chaining into an n-bit equals comparator has carry in and carry out terminals with three MOSFETs and an inverter connected to pass through a high carry in voltage to the carry out terminal but to allow the comparison of the first and second bits in additional circuitry to determine the carry out voltage with a low carry in voltage. Further MOSFETs, in one P channel and one N channel pair, are interconnected and provided with the first bit, second bit and complement of the second bit to detect equality of the first and second bits. The circuit uses a small number of transistors per bit for the comparison.
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