| 摘要 |
PURPOSE:To bring a series of data extending over plural units to a DMA transfer at high speed from one source device, by counting a unit transfer operation of a data bus length portion executed by a DMA controller, by a counting part, and continuing a DMA request by a DMA request continuing part until a count value of the counting part becomes a prescribed value. CONSTITUTION:In a byte mode, in response to a transfer operation of a one-byte portion executed by a DMA controller 18, a DMA sub-controller 24 repeats and generates another DMA request signal by a necessary number of times as a hardware and outputs it to the DMA controller 18. In such a way, until the next data of a one-byte portion is transferred after the data of a one-byte portion has been transferred, it is unnecessary that a CPU 12 executes another DMA request to an input device 16 side by a processing as a software, a series of data extending over plural units can be transferred at a high speed, and even if it is tried to reset immediately a timer data counted by a timer part 22 due to existence of an adjacent silent part on a tape, a data transfer of 16 bits can be completed surely before the timer data is varied, and no transfer miss is generated. |
