发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
摘要 |
PURPOSE:To eliminate occurrence of latch up completely, by employing a dielectric isolation technique for insulation between a vertical type MOS and a horizontal type MOS in an output circuit part of high breakdown strength. CONSTITUTION:A dielectric isolation substrate on an output circuit part of high breakdown strength is composed mostly of a polycrystalline semiconductor substrate 13. P-type single-crystal semiconductor regions 15 to 17 are buried insularly with a dielectric film 14 in between on a main surface 11 side of this substrate. Two n-type layers and p<+> type layers serving as sources in the n-type layers are formed in the region 15 so as to compose a vertical type p-MOS. Two n<+>type layers serving as a source and a drain respectively are formed in the region 17 so as to compose a horizontal type n-MOS. P-type single-crystal layers 15' and 16' are formed to penetrate through dielectric films on the bottom parts in the region 15 and 16 and extended to an electrode layer 8 formed on a main surface 12 of this substrate. Such composition realizes good endurance to latch up and high integrity. |
申请公布号 |
JPS644058(A) |
申请公布日期 |
1989.01.09 |
申请号 |
JP19870157704 |
申请日期 |
1987.06.26 |
申请人 |
HITACHI LTD |
发明人 |
SUDA KOICHI;TSUKUDA KIYOSHI;KARIYA TADAAKI;MATSUZAKI HITOSHI |
分类号 |
H01L21/762;H01L21/76;H01L21/8238;H01L27/08;H01L27/088;H01L27/092;H01L29/78 |
主分类号 |
H01L21/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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