| 摘要 |
PURPOSE:To obtain a diagnostic type clock control circuit which can point out the fault areas by always monitoring the fault of the circuit after diagnosing a clock system for each module to which the clocks are distributed. CONSTITUTION:A phase advance diagnostic signal (h) received from a terminal of a diagnostic processor is set at 1 and a diagnostic instruction signal (f) received from another terminal is set at 1 in the timing t2. Both signals (h) and (f) are supplied to a diagnostic circuit 6. An AND gate QP secures an AND between both signals (h) and (f) and supplies 1 to the input 2B of a sector JP. At the same time, the signal (h) is supplied to the input SEL of the sector JP via an OR gate GP. A phase advance report signal (j) is supplied to a delay control circuit to advance the phase of the clock delivered to a logical module against a reference clock. The logical module detects this phase advance and sets a phase advance signal (e) at 1 in the timing t3. The signal (e) is supplied to the circuit 6 and an AND gate FP secures an AND between both signals (e) and (h) to deliver a diagnostic report signal (k) via an OR gate HP. The signal (k) is supplied to the diagnostic processor via a register LP for diagnosis of the clock systems of a clock generating module and a diagnostic module. |
