| 摘要 |
PURPOSE:To obtain small-sized, simple constitution by providing a decentralized frame synchronization system with a memory where data are readable and writable, an address instructing means, and a data control means. CONSTITUTION:When this data processor is applied to the synchronizing pattern detection part 1 of a frame synchronization part, buffer memories 104A and 104B and a connecting line 105 constitute a data control means together with a clock generating means which supplies a clock to an (m)-scale counter 103 as the address instructing means. A bit train of multiplexing data arrives from a line 101. This data control means reads data out of a RAM 103 according to the address that the (m)-scale counter 103 outputs, deletes its most significant digit bits, and carrys its respective digit data, and data arriving from the line 101 is added as the least significant digit bit to constitute data having with data length equal to the data length n-1 of the RAM 10, thereby storing it in the RAM 102 according to the address that the (m)-scale counter 103 outputs. |
