发明名称 BUS CONTROLLER FOR MULTIPROCESSOR
摘要 PURPOSE:To properly execute data processing by means of a master processor by restricting the access time of a main memory by a processor except a master processor. CONSTITUTION:A master/slave constitution is composed of a main processing unit 1 including the master processor and a sub-processing unit 2 including a slave processor, and the sub-processing unit 2 transmits various control signals to an external processor 15 provided to a peripheral unit 3 through a control bus. Then when the processor except the master processor requests an access to the main memory 4, the master processor is made to be an operation stopping state and restricts the time for delivering an access right to the other processor within the prescribed time. Thus the utilization time of the main memory can be efficiently managed and the operation by the multiprocessor constitution can be accelerated.
申请公布号 JPS642159(A) 申请公布日期 1989.01.06
申请号 JP19870158387 申请日期 1987.06.25
申请人 MATSUSHITA ELECTRIC WORKS LTD 发明人 TAKERA JOJI
分类号 G06F15/16;G06F13/16;G06F13/362;G06F15/173 主分类号 G06F15/16
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