| 发明名称 |
Method of making a power IC structure with enhancement and/or CMOS logic |
| 摘要 |
A process for fabricating a power IC structure which includes the following masking steps: 1. CMOS P well mask 2. JFET (short-channel implant) mask 3. Field oxide growth mask 4. Deep P+ mask 5. Polysilicon mask 6. DMOS P well mask 7. n-/n+ mask 8. Contact window mask 9. Metalization mask 10. Overglass mask.
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| 申请公布号 |
US4795716(A) |
申请公布日期 |
1989.01.03 |
| 申请号 |
US19870064133 |
申请日期 |
1987.06.19 |
| 申请人 |
GENERAL ELECTRIC COMPANY |
发明人 |
YILMAZ, HAMZA;WRATHALL, ROBERT S.;CHANG, MIKE F.;HODGINS, ROBERT G. |
| 分类号 |
H01L21/60;H01L21/82;H01L21/8234;(IPC1-7):H01L21/22;H01L21/306;H01L21/265 |
主分类号 |
H01L21/60 |
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