| 摘要 |
Reference clock signals of the same frequency as that of image scanning clock signals are applied to a shift register, and corrective clock signals of a higher frequency than that of the reference clock signals C0 are applied as shift clock signals to the shift register, which generates n output signals C1, C2, . . . Cn (n>/=2) which are applied to delay circuits. The delay circuits produce pulse signal groups which are successively delayed DELTA t in phase. Assuming that the frequency of the reference clock signals is f0 MHz and the frequency of the corrective clock signals is nxf0 MHz, the above phase DELTA t is selected to meet meets the relationship: <IMAGE> One of the pulse signal groups thus delayed DELTA t in phase is selected as image scannnig clock signals in response to an output signal from a light sensor that detects a scanning beam for synchronizing main scanning cycles.
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